Delay Optimum And Area Optimal Mapping Of k-LUT Based FPGA Circuits
نویسنده
چکیده
The paper presents several improvements to our synthesis platform Xsynth that was developed targeting advanced logic synthesis and technological mapping for k-LUT based FPGAs. Having implemented an efficient exhaustive k-feasible cone generator it was targeted delay optimum mapping and optimal area. Implemented algorithm can use common unit-delay model and, the more general, the edge-delay model. The last model allows arbitrary delay values assignments to each branch of a circuit net. Such arbitrary delay values my reflect estimates of placement and routing delays. Powerful heuristics targeting minimal area (number of used LUTs in the mapped network) allow determinations of delay minimum solutions but having low used area.
منابع مشابه
On K-LUT Based FPGA Optimum Delay and Optimal Area Mapping
We developed, using structures from MV-SIS, an application dedicated to K-LUT based FPGA synthesis, named Xsynth. Main component of it, levelMap the mapping program, was implemented using the minDepth algorithm. The mapping program was instrumented in order to study and evaluate different heuristics involved in establishing best approach to find optimum delay and optimal area mapping. We did ru...
متن کاملPower-Aware, Depth-Optimum and Area Minimization Mapping of K- LUT Based FPGA Circuits
This paper introduces an efficient application intended for mapping under complex criteria applied to K-LUT based FPGA implemented circuits. This application is based on an algorithm that was developed taking into consideration a significant design factor power consumption. Power consumption is considered in addition to other design factors that are traditionally used. To increase performance, ...
متن کاملHeuristic Performance Optimal and Power Conscious for K-LUT Based FPGA Technology Mapping
In this paper is presented a new approach for decreasing the power consumption in LUT based FPGA implemented circuits. The attempt is based on reducing logic activity among LUTs. In order to achieve this target it was used the probability approach that estimates the dynamic logic activity of each line in the circuit. Traversing circuits from primary inputs lines to the primary output lines, ste...
متن کاملFlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
This paper represents pioneering work in the area of technology mapping for FPGAs and presents a theoretical breakthrough by solving the LUT-‐based FPGA technology mapping problem for depth minimization optimally in polynomial time. The key idea was to model the LUT mapping problem as the computation of a minimum-‐height, K-‐feasible cut. This was the first global formulation of the LUT mapp...
متن کاملAn Efficient LUT Design on FPGA for Memory-Based Multiplication
An efficient Lookup Table (LUT) design for memory-based multiplier is proposed. This multiplier can be preferred in DSP computation where one of the inputs, which is filter coefficient to the multiplier, is fixed. In this design, all possible product terms of input multiplicand with the fixed coefficient are stored directly in memory. In contrast to an earlier proposition Odd Multiple Storage ...
متن کامل